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EDA Alert e-Newsletter
PlanetEE - www.planetee.com
December 16, 2002
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Today's Table of Contents:
1. Viewpoint  - The Future Of Electronic Design Is Low Power
2. Ansoft Enhances Simplorer SV Design Tool
3. DAC, ISSCC Accepting Student Design Contest Entries
4. Aptix Extends Pre-Silicon Prototyping
5. Cadence Delivers OpenAccess Source Code
6. Support Grows For OpenVera Assertions
7. OCP-IP Celebrates 1st Birthday
8. Happenings
   DesignCon 2003
   Design and Verification Conference and Exhibition
    (DVCon, formerly HDLCon)
   DATE 03

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1. Viewpoint - Exclusive to EDA Alert
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The Future Of Electronic Design Is Low Power
By James Lee, President, The ASIC Group

Even if you're not designing a battery-powered device, you may
need to pay attention to power consumption. For line-powered
devices the power budget may not be dictated by getting the power
in, but rather by dissipating the heat. As the heat dissipated by
a chip increases, so does the cost of keeping it cool. Ceramic
packages are the first step in combating higher power
consumption. If the heat cannot be managed by a ceramic package
alone, heat sinks or fans may be needed. Each of these
heat-dissipating measures incrementally adds cost. In a consumer
device the cost difference between a ceramic package and a
plastic package could make or break the targeted price point.

The silicon content of everyday devices continues to increase but
where is the focus on low-power design techniques and tools? One
of the most common power-saving techniques is to use multiple
clock domains, each tailored to functional units within the chip.
However, tool support for this basic technique is limited. The
synthesis-based techniques of the 1990s are not as conducive to
power minimization as were the hand-crafted techniques which,
decades ago, brought us digital watches that ran for more
than a year on a single (less powerful) battery and with larger
internal power use per transistor.

Design tools and techniques must change to help design and
analyze chips with multiple clock domains. Today there are some
simple clock-gating tricks that synthesis tools can use to
slightly reduce power, but the big power savings are achieved
through clever architectures.

Experience is the best tool the SoC architect has available for
power optimization. Experience has taught us to partition logic
into separate clock domains, disabling clocks to idle parts of
the system and slowing clocks to match lower data rates.
Experienced designers break long combinatorial paths with
registers to minimize switching. While the basic technique is
time-proven, there is little to guide the details of the architecture.

Partitioning the design into multiple clock domains presents its
own set of problems. If the clocks are not synchronous or
harmonically related, the designer must ensure that
synchronization logic is used between domains. If the clock
domains are synchronous or harmonically related, the designer may
desire to pass data between the domains directly. Doing so
requires that the clock edges be tightly aligned. This may present
a problem for clock-tree synthesis tools,particularly when some
clock domains may be heavily loaded and others may not. Analyzing
timing between multiple clock domains adds more complication.  The
non-synchronous domains must be checked to ensure synchronizers
on all crossings.  The synchronous domains require analysis for setup
and hold at each crossing. Multi-cycle paths must be checked between
harmonically related paths. Care must be taken when passing data
from a fast domain to a slow domain to make sure it is not lost.

Some of the structural checks for data passing between domains
can be automated through static RTL verification tools.
Fortunately, the leading static RTL verification tools, Real
Intent's Verix and Verplex's BlackTie, both address clock domain
crossing.

Once the circuit is properly partitioned and all clock crossings
have been checked, how can the power budget be analyzed? Most
power estimation tools work only at the gate level and then with
mixed results. A recent analysis of an ultra-low-power medical
chip designed by the ASIC Group estimated the static power in
excess of the measured dynamic power.

The EDA industry and ASIC/SoC designers are faced with a power
crisis and it can't be solved by raising taxes, building
additional power plants or installing compact fluorescent light
bulbs. It needs the serious, large-scale attention of EDA vendors
and designers.  Tools and techniques must evolve from the single
clock synthesis and timing analysis methodologies of the 1990s.
Power estimation and analysis tools must become as commonplace as
logic simulators in the ASIC/SoC design process to fight this
emerging power crisis.

Contact the author at: jml@ASICgroup.com

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2. News
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Ansoft Enhances Simplorer SV Design Tool
Ansoft Corp. has released Simplorer SV version 6, a free
downloadable version of Simplorer, Ansoft's mixed-domain systems
design software. The new version integrates VHDL-AMS, a standard
modeling language for analog mixed-signal design, within
Simplorer's popular graphical user environment.

Users can now perform simulations using VHDL-AMS alone or in
combination with circuits, block diagrams, state machines, and
Simplorer's other modeling languages. Ansoft also has added DC
and AC analysis capabilities to the software, making it an
attractive alternative to Spice simulation.

SIMPLORER SV version 6.0, is available for download at:

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3. News
*******
DAC, ISSCC Accepting Student Design Contest Entries
Submissions are now being accepted for the Design Automation
Conference (DAC) and IEEE International Solid State Circuits
Conference (ISSCC) Student Design Contest. The deadline for
submissions is Friday, December 20, 2002.  Awards will be
presented at the 40th annual DAC, held June 2-6, 2003, at
the Anaheim Convention Center in Anaheim, California.

The Student Design Contest, sponsored by numerous electronics
companies, promotes excellence in the design of electronic
systems. The contest is accepting entries of both integrated
circuits and electronic systems and will award a total of $20,000
in recognition of undergraduate and graduate students who
demonstrate excellence in the development of operational and
conceptual designs.  Winners will be invited to present their
work at both DAC 2003 and ISSCC 2004. Co-chairs for this year's
contest include: Steven P. Levitan, University of Pittsburgh;
Alan Mantooth, University of Arkansas; and David Greenhill, Sun
Microsystems. Additional information, and last year's winners,
can be found at:

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4. News
*******
Aptix Extends Pre-Silicon Prototyping
A complete RTL-to-pre-silicon prototype flow is offered by
Aptix's Prototype Studio, a product line aimed at developers of
custom multi-FPGA printed circuit boards. Prototype Studio, which
includes Aptix's Design Pilot, supports partitioning a monolithic
SoC design across multiple FPGAs. It works within the pin
constraints of the FPGAs, mapping SoC constructs such as gated
clocks into structures more appropriate for FPGAs, and debugging
within the prototype when problems are revealed.

Prototype Studio is available in three forms. Prototype
Studio/PCB is available to designers targeting only hardwired
PCBs. Prototype Studio/Pro supports Aptix's traditional
reconfigurable prototyping products, System Explorer and
Software Integration Station. And Prototype Studio/Enterprise
supports all hardware targets. Pricing starts at $79,500 for a
one-year license. All versions are shipping now.
 
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5. News
*******
Cadence Delivers OpenAccess Source Code
In a major milestone for the OpenAccess Coalition's efforts,
Cadence Design Systems has delivered to the Coalition source code
for the OpenAccess reference database implementation. OpenAccess
is intended to enable electronics companies to more quickly and
easily create integrated design flows of tools from multiple
vendors and internal technology. The database will allow tool
uses to connect to an industy-standard platform. For its part,
Cadence plans to adopt OpenAccess as its standard API and unified
database.

Beta tests of the source code enabled Cadence and the Coalition
to improve and extend the reference database by rooting out bugs
and uncovering limitations. The resulting code, which has been
delivered ahead of schedule, is said to exceed the requirements
of the original agreement.

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6. News
*******
Support Grows For OpenVera Assertions
Synopsys has announced the availability of seven new third-party
verification intellectual property (IP) offerings based on
OpenVera Assertions (OVA). Designed for checking compliance with
widely adopted and emerging protocols, OVA verification IP are
reusable modules that accelerate the development of a complete
verification environment, improving overall efficiency and
productivity for design and verification engineers. With
the release of these OVA verification IP offerings, third-party
IP providers Cold Spring Engineering (Utopia 2.0, SPI 4.2), nSys
(PCI Express, PCMCIA, UART, Parallel 1284) and Silicon Interfaces
(Bluetooth, USB 2.0) join the design verification and service
providers who support OVA for customers seeking an
assertion-based methodology to overcome the verification
bottleneck.

*******
7. News
*******
OCP-IP Celebrates 1st Birthday
The Open Core Protocol International Partnership (OCP-IP), an
industry association delivering a common standard for
intellectual property core interfaces, or sockets, that
facilitate "plug and play" SOC design, has marked its first
anniversary. Among its accomplishments have been: a membership
roster rapidly approaching the 50 member mark, the kick-off
of a University program, a highly successful trade show and
conference program, and six active working groups covering
Marketing, Vision, Specification, System Level, Memory Semantics,
and Verification.

The organization also anticipates the release of the 2003 OCP
specification in early Q1 of 2003. The enhanced specification
will include: a model for write transfers which provide for
precise end-to-end-responses; an enhanced burst model that
provides both burst length and packet style transfers; support
for specification endianness; support for user-defined, in-band
command data and response extensions; even lighter-weight OCP
interfaces with read only/write only/FIFO style IP cores; and
support for lazy memory synchronization.

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8. Happenings
*************

DesignCon 2003
Santa Clara Convention Center, Santa Clara, CA
January 27-30, 2003

Design and Verification Conference and Exhibition (DVCon,
formerly HDLCon)
Doubletree Hotel, San Jose, CA
February 24-26, 2003

DATE 03
ICM, Munich, Germany
March 3-7, 2003

EDA ALERT e-NEWSLETTER CONTACTS
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EDA Technology Editor, Electronic Design: David Maliniak 

Advertising/Sponsorship Opportunities:
Bill Baumann, bbaumann@penton.com

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